[最も選択された] verilog ifdef parameter 239078-Verilog define parameter 차이

If the macro has not been defined, the compiler compiles the code (if any) following the optional `else directive You can control what code is compiled by choosing whether to define the text macro, either with `define or with define The `endif directive marks the end of the conditional code Example ifdef 1moduleifdef ();

Verilog define parameter 차이- Syntax `ifdef macro_name `endif The macros can either be defined using `define directive or be passed as a parameter with the compile command using the define option `ifndef This directive is just the opposite of the `ifdef directive This directive will compile the underlying code only when the macro is not defined`endif end always @(posedge b)